The increasing demand in exchanging data faster in datacenters, enterprise server/storage, and wireless infrastructure applications has led the proliferation of high-speed interface protocols and devices such as transmitters, receivers, and mid channel signal conditioner that are compliant to industrial standard such as IEEE 802.3a/g, USB3, HDMI and others. As data-rate increase into multi-Giga bit realm, channel loss, reflection, jitter, and cross-talk cause a dominant effect on the system performance. It is crucial for a high-speed serial link system designer to identify the right devices to meet the system performance requirements and at the same time reduce power, footprint size, and total bill of material (BOM) cost.
Referring to FIG. 1, a conventional signal flow diagram 100 for a typical high-speed serial link transmitter-receiver pair is illustrated. The typical signal flow 100 for high-speed serial link system includes a transmitter 110 as a signal source, a channel that comprised of transmitter package 120, transmitter site connector 130, PCB trace 140, receiver site connector 150, receiver package 160, and a receiver 170 to recover the signal.
Referring to FIG. 2, a conventional signal flow diagram 200 for a typical high-speed serial link transmitter-receiver pair with signal strength boosting components is illustrated. Signal flow diagram 200 includes transmitter 110, upstream channel 115, which includes components such as transmitter package 120 and transmitter site connector 130. A downstream channel 155 including a receiver site connector 150 and a receiver package 160, and a receiver 170. A signal conditioner (SigCon) component 145 is added in the path to boost signal strength to improve signal condition due to unavoidably high insertion loss.
High-speed serial link devices such as transmitters, receivers, and mid-channel signal conditioners illustrated in FIGS. 1-2 are proliferating in the industry due to increasing demand for bandwidth. A myriad of integrated circuits (ICs) are available in the market for high-speed interface and this creates a significant challenge for high-speed serial link system designers to identify the optimal IC that can meet the system performance requirements and at the same time reduce power, footprint size, and total BOM cost. A typical interface part selection process starts by screening through hundreds of datasheets from IC manufacturers' websites to identify potential solutions. This is followed by contacting the IC vendor for an evaluation to help identify the optimal device(s). Typically, in transmitter selection process, the bandwidth, jitter performance, and equalization characteristics are the main consideration. For receiver selection, there are multiple facets of equalization needs to be considered such as Continuous Time Linear Equalization (CTLE) and Decision Feedback Equalization (DFE).
It is a daunting task to design a high-speed serial link system as it involves cross-disciplinary technical knowledge such as microwave transmission theory, analog and digital compensation theory, and signal integrity theory. For mid-channel devices, various functions such as re-drivers, re-timers, or mux/fanouts can be carefully considered to select the most appropriate device. In addition to the selection process, system engineers need to be able to quickly validate through simulations that the identified serial-link device(s) meets their system performance requirements. This process can take weeks to complete, making it difficult to effectively compare multiple solutions in a timely manner.